Presentation 2011-07-22
Analog Design Optimization with g_m/I_D Lookup Table Methodology
Takayuki KONISHI, Takaaki NAGASHIMA, Ben PATRICK, Takana KAHO, Shoichi MASUI,
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Abstract(in English) We propose a design optimization for analog circuits based on g_m/I_D lookup table design methodology. The features of using this methodology are 1) providing a superior initial circuit parameter set to a numerical design centering/ sizing tool for analog circuits, 2) providing a SPICE analog parameter verification method related to a design methodology.
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Keyword(in English) analog design methodology / low power design / SPICE parameters
Paper # ICD2011-32
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Conference Date 2011/7/14(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Analog Design Optimization with g_m/I_D Lookup Table Methodology
Sub Title (in English)
Keyword(1) analog design methodology
Keyword(2) low power design
Keyword(3) SPICE parameters
1st Author's Name Takayuki KONISHI
1st Author's Affiliation Tohoku University()
2nd Author's Name Takaaki NAGASHIMA
2nd Author's Affiliation Tohoku University
3rd Author's Name Ben PATRICK
3rd Author's Affiliation Tohoku University
4th Author's Name Takana KAHO
4th Author's Affiliation NTT Network Innovation Laboratories
5th Author's Name Shoichi MASUI
5th Author's Affiliation Tohoku University
Date 2011-07-22
Paper # ICD2011-32
Volume (vol) vol.111
Number (no) 151
Page pp.pp.-
#Pages 6
Date of Issue