Presentation 2011-07-22
A Diagnosis Testbench of Analog IP Cores Against On-Chip Environmental Disturbances
Yuuki ARAGA, Takushi HASHIDA, Shinichiro UEYAMA, Makoto NAGATA,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Analog IP cores exhibit a multivariate response to dynamic variations of an operation environment, that are typically represented by power and substrate voltage changes. A testbench provides a silicon area to embed and diagnose custom IP cores with power delivery and substrate networks, where the area is surrounded by on-chip precision waveform capturing and configurable power and substrate noise generation circuits. The coefficients of noise propagation and noise coupling are quantitatively derived for fabless IP cores processed in a target technology.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Mixed signal LSI / On-chip testing / Testbench
Paper # ICD2011-29
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Committee ICD
Conference Date 2011/7/14(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Diagnosis Testbench of Analog IP Cores Against On-Chip Environmental Disturbances
Sub Title (in English)
Keyword(1) Mixed signal LSI
Keyword(2) On-chip testing
Keyword(3) Testbench
1st Author's Name Yuuki ARAGA
1st Author's Affiliation Graduate school of system informatics, Kobe University()
2nd Author's Name Takushi HASHIDA
2nd Author's Affiliation Graduate school of system informatics, Kobe University
3rd Author's Name Shinichiro UEYAMA
3rd Author's Affiliation Graduate school of system informatics, Kobe University
4th Author's Name Makoto NAGATA
4th Author's Affiliation Faculty of Engineering, Kobe University
Date 2011-07-22
Paper # ICD2011-29
Volume (vol) vol.111
Number (no) 151
Page pp.pp.-
#Pages 6
Date of Issue