| Presentation | 2011-07-21 64ch Neural Recording Chip for Human Brain-Machine Interface Takeshi YOSHIDA, Katsuya SUEISHI, Masahiro ONO, Hiroshi ANDO, Yoshitaka MURASAKA, Atsushi IWATA, Kojiro MATSUSHITA, Masayuki HIRATA, Takafumi SUZUKI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | To improve the Quality of Life (QoL) of the severely disabled people, the brain-machine interface (BMI) and multi-channel neural recording chips have been proposed. We developed the 64ch neural recording chip which consists of low-noise amplifier and 12bit SAR-ADC. The chip was implemented in 0.18(im standard CMOS process. The low-noise amplifier achieved a selectable voltage gain from 40 to 80dB, variable high-pass cutoff frequency from 0.04 to 30Hz, variable low-pass cutoff frequency from 100 to 1kHz and input referred noise of 2.5μVrms (～100Hz). The ENOB of 12bit SAR-ADC was 10.5bit at 32kSps operation. The total power consumption of proposed chip was 5mW at a supply voltage of 1.8V. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Brain machine interface / BMI / Neural recording / Eow noise amplifier / Adjustable pseudo-resistor / cascade MOSFETs / ADC |
| Paper # | ICD2011-23 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2011/7/14(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 64ch Neural Recording Chip for Human Brain-Machine Interface |
| Sub Title (in English) | |
| Keyword(1) | Brain machine interface |
| Keyword(2) | BMI |
| Keyword(3) | Neural recording |
| Keyword(4) | Eow noise amplifier |
| Keyword(5) | Adjustable pseudo-resistor |
| Keyword(6) | cascade MOSFETs |
| Keyword(7) | ADC |
| 1st Author's Name | Takeshi YOSHIDA |
| 1st Author's Affiliation | Graduate School of Advanced Sciences of Matter, Hiroshima University() |
| 2nd Author's Name | Katsuya SUEISHI |
| 2nd Author's Affiliation | Graduate School of Advanced Sciences of Matter, Hiroshima University |
| 3rd Author's Name | Masahiro ONO |
| 3rd Author's Affiliation | A-R-Tec |
| 4th Author's Name | Hiroshi ANDO |
| 4th Author's Affiliation | Graduate School of Advanced Sciences of Matter, Hiroshima University |
| 5th Author's Name | Yoshitaka MURASAKA |
| 5th Author's Affiliation | A-R-Tec |
| 6th Author's Name | Atsushi IWATA |
| 6th Author's Affiliation | A-R-Tec |
| 7th Author's Name | Kojiro MATSUSHITA |
| 7th Author's Affiliation | Department of Neurosurgery, Osaka University Medical School |
| 8th Author's Name | Masayuki HIRATA |
| 8th Author's Affiliation | Department of Neurosurgery, Osaka University Medical School |
| 9th Author's Name | Takafumi SUZUKI |
| 9th Author's Affiliation | Graduate School of Information Sciences and Technology, The University of Tokyo |
| Date | 2011-07-21 |
| Paper # | ICD2011-23 |
| Volume (vol) | vol.111 |
| Number (no) | 151 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |