Presentation | 2011-07-13 High-Throuput Bit-Slice Multipliers Using SFQ Circuits Yohei NARUSE, Nobutaka KITO, Naofumi TAKAGI, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Single flux quantum (SFQ) circuits are expected as next-generation circuits. Arithmetic circuits using SFQ circuits have been designed based on bit-serial structure. When the bit width of input data increases, the number of cycles to input data increases. In this report, we propose a multiplier operating at high frequency based on bit-slice architecture. Bit-slice multipliers have feedback loops, and the clock frequency depends on the size of these loops. In the proposed bit-slice multiplier, we minimize the feedback loops. We show that the throughput of the proposed bit-slice multiplier is improved in proportion to bit-slice width, and that the hardware cost of the proposed bit-slice multiplier increases in proportion to bit-slice width. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | SFQ circuit / reconfigurable data-path / multiplier / bit-slice |
Paper # | SCE2011-9 |
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Committee | SCE |
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Conference Date | 2011/7/6(1days) |
Place (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Superconductive Electronics (SCE) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | High-Throuput Bit-Slice Multipliers Using SFQ Circuits |
Sub Title (in English) | |
Keyword(1) | SFQ circuit |
Keyword(2) | reconfigurable data-path |
Keyword(3) | multiplier |
Keyword(4) | bit-slice |
1st Author's Name | Yohei NARUSE |
1st Author's Affiliation | Kyoto University() |
2nd Author's Name | Nobutaka KITO |
2nd Author's Affiliation | Kyoto University |
3rd Author's Name | Naofumi TAKAGI |
3rd Author's Affiliation | Kyoto University |
Date | 2011-07-13 |
Paper # | SCE2011-9 |
Volume (vol) | vol.111 |
Number (no) | 130 |
Page | pp.pp.- |
#Pages | 6 |
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