Presentation | 2011-07-13 Ultra-Low-Power Superconducting Logic Circuits using Adiabatic Quantum Flux Parametron Nobuyuki YOSHIKAWA, Dan OZAWA, Kohei EHARA, Yuki YAMANASHI, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In this study, ultimate-low-power adiabatic quantum flux parametron (QFP) logic is proposed. In our approach, nonhysteretic QFPs are operated very slowly to prevent non-adiabatic energy dissipation occurring during switching events. The parameter condition that the QFP operates in the adiabatic mode was investigated and their energy dissipation per switch was evaluated by circuit simulations. The dynamic energy dissipation of the designed adiabatic QFP gate is estimated to be 6% of Ι_0Φ_0 when the rise and fall time is 100 ps, which can be further reduced by decreasing circuit inductances. The robustness of the adiabatic QFP gates, including a NOT gate, a majority gate and a fan-out gate, was also investigated by calculating their bias margins. Three stages of adiabatic QFP NOT gates were fabricated using a Nb Josephson integrated circuit process and their operation was successfully confirmed. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Superconducting integrated circuits / Josephson circuits / SFQ circuits / QFP / Adiabatic circuits |
Paper # | SCE2011-8 |
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Conference Information | |
Committee | SCE |
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Conference Date | 2011/7/6(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Superconductive Electronics (SCE) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Ultra-Low-Power Superconducting Logic Circuits using Adiabatic Quantum Flux Parametron |
Sub Title (in English) | |
Keyword(1) | Superconducting integrated circuits |
Keyword(2) | Josephson circuits |
Keyword(3) | SFQ circuits |
Keyword(4) | QFP |
Keyword(5) | Adiabatic circuits |
1st Author's Name | Nobuyuki YOSHIKAWA |
1st Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University() |
2nd Author's Name | Dan OZAWA |
2nd Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
3rd Author's Name | Kohei EHARA |
3rd Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
4th Author's Name | Yuki YAMANASHI |
4th Author's Affiliation | Department of Electrical and Computer Engineering, Yokohama National University |
Date | 2011-07-13 |
Paper # | SCE2011-8 |
Volume (vol) | vol.111 |
Number (no) | 130 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |