| Presentation | 2011-07-28 Proposal for High Efficient DVS Using Adaptive Redundancy of FUs Yukihiro SASAGAWA, Jun YAW, Takashi NAKADA, Yasuhiko NAKASHIMA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, the well-known low power technology DVS(Dynamic Voltage Scaling) is aggressively applied to processors with Razor Flip-Flops in which the voltage is down scaled to near critical setup timing level for a maximum power consumption reduction. However, the conventional Razor and DVS combinations cannot well tolerate error rate variations caused by IR-drops and environment changes. At the near critical setup timing point, even a small error rate change will result in sharp performance degradation. For this purpose, we propose redundant data-paths to provide an additional coverage for error rate variation in a processor with Razor FFs. In detail, the redundant data-paths use multi-cycle calculation to support original single cycle execution to prevent long pipeline hazards after setup errors. Only one cycle will be used to recover from erroneous execution. We explore the application of this proposal on a multiple FUs (Functional units) structure. Our performance model indicates that as compared to the traditional method, the proposed DVS scheme can reduce 40% performance loss and 90% energy increase under the condition that the unexpected IR-drop reaches 10% of source voltage. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FU array / adaptive redundancy / setup error recovery / DVS / low power / AVF |
| Paper # | DC2011-15 |
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| Committee | DC |
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| Conference Date | 2011/7/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Proposal for High Efficient DVS Using Adaptive Redundancy of FUs |
| Sub Title (in English) | |
| Keyword(1) | FU array |
| Keyword(2) | adaptive redundancy |
| Keyword(3) | setup error recovery |
| Keyword(4) | DVS |
| Keyword(5) | low power |
| Keyword(6) | AVF |
| 1st Author's Name | Yukihiro SASAGAWA |
| 1st Author's Affiliation | Nara Institute of Science and Technology(NAIST)() |
| 2nd Author's Name | Jun YAW |
| 2nd Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| 3rd Author's Name | Takashi NAKADA |
| 3rd Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| 4th Author's Name | Yasuhiko NAKASHIMA |
| 4th Author's Affiliation | Nara Institute of Science and Technology(NAIST) |
| Date | 2011-07-28 |
| Paper # | DC2011-15 |
| Volume (vol) | vol.111 |
| Number (no) | 164 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |