Presentation 2011-06-30
Architecture Development of Foreground Segmentation LSI Using GMM
Ryo YAGI, Tomohito KAJIMOTO, Takao NISHITANI,
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Abstract(in English) The main part of an IP-CORE based on a Foreground Segmentation algorism which reduces a lot of the processing amount by using Walsh Transform domain, is designed. The designed part is on the multi-resolution GMM for HDTV pictures. The designed architecture employs application specific multi-processor approach for GMM. Every processor element employs pipeline processing where the inclusion judgment of Gaussian is carried out so as not to disturb pipeline processing, by introducing simple speculation steps. These steps can be derived from the conditional processing equations. The designed IP-CORE can be estimated to realize real-time HDTV Foreground Segmentation at the clock speed of 100MHz with less than three HDTV frame memories.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Foreground Segmentation / GMM / Multi-thread Parallel Computation / Pipeline / Speculation Implement
Paper # CAS2011-5,VLD2011-12,SIP2011-34,MSS2011-5
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Conference Date 2011/6/23(1days)
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Registration To Mathematical Systems Science and its applications(MSS)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Architecture Development of Foreground Segmentation LSI Using GMM
Sub Title (in English)
Keyword(1) Foreground Segmentation
Keyword(2) GMM
Keyword(3) Multi-thread Parallel Computation
Keyword(4) Pipeline
Keyword(5) Speculation Implement
1st Author's Name Ryo YAGI
1st Author's Affiliation Tokyo Metropolitan University()
2nd Author's Name Tomohito KAJIMOTO
2nd Author's Affiliation Tokyo Metropolitan University
3rd Author's Name Takao NISHITANI
3rd Author's Affiliation Tokyo Metropolitan University
Date 2011-06-30
Paper # CAS2011-5,VLD2011-12,SIP2011-34,MSS2011-5
Volume (vol) vol.111
Number (no) 105
Page pp.pp.-
#Pages 6
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