Presentation | 2011-06-30 Electrical Property Improvement by Inserting a Buffer Layer in Impurity-Doped ZnO Transparent Electrodes Prepared by Magnetron Sputtering Depositions Jun-ichi NOMOTO, Tomoyasu HIRANO, Toshihiro MIYATA, Tadatsugu MINAMI, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Improvements of obtainable lowest resistivity as well as spatial resistivity distribution on the substrate surface in Al- or Ga-doped ZnO (AZO or GZO) thin films prepared by a newly developed deposition technique using an MS apparatus were successfully achieved by inserting a very thin buffer layer between the thin films and the glass substrates. The buffer layer was deposited by sputtering a target surface that was more strongly oxidized than is usually the case during conventional d.c. or r.f. superimposed d.c. magnetron sputtering (dc-MS or rf+dc-MS) depositions optimized to obtain lower resistivity. A minimum resistivity of approximately 3×10^<-4>Ωcm was obtained in 150-nm-thick-GZO and -AZO thin films that had a 10-nm-thick-buffer layer prepared at 200℃. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | ZnO / AZO / GZO / Magnetron sputtering / Buffer layer |
Paper # | EMD2011-11,CPM2011-47,OME2011-25 |
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Conference Information | |
Committee | CPM |
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Conference Date | 2011/6/23(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Component Parts and Materials (CPM) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Electrical Property Improvement by Inserting a Buffer Layer in Impurity-Doped ZnO Transparent Electrodes Prepared by Magnetron Sputtering Depositions |
Sub Title (in English) | |
Keyword(1) | ZnO |
Keyword(2) | AZO |
Keyword(3) | GZO |
Keyword(4) | Magnetron sputtering |
Keyword(5) | Buffer layer |
1st Author's Name | Jun-ichi NOMOTO |
1st Author's Affiliation | O.E.Device System R&D Center, Kanazawa I.T.() |
2nd Author's Name | Tomoyasu HIRANO |
2nd Author's Affiliation | O.E.Device System R&D Center, Kanazawa I.T. |
3rd Author's Name | Toshihiro MIYATA |
3rd Author's Affiliation | O.E.Device System R&D Center, Kanazawa I.T. |
4th Author's Name | Tadatsugu MINAMI |
4th Author's Affiliation | O.E.Device System R&D Center, Kanazawa I.T. |
Date | 2011-06-30 |
Paper # | EMD2011-11,CPM2011-47,OME2011-25 |
Volume (vol) | vol.111 |
Number (no) | 109 |
Page | pp.pp.- |
#Pages | 5 |
Date of Issue |