Presentation 2011-06-09
Power Reduction of MIMO-OFDM Receiver Circuits Using Dynamic MIMO Detection Techniques
Nozomi MIYAZAKI, Shingo YOSHIZAWA, Yoshikazu MIYANAGA,
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Abstract(in English) This presents power reduction for MIMO-OFDM receiver circuits using dynamic MIMO detection techniques. MIMO-OFDM imposes MIMO detection to separate received signals multiplexed in the transmitter, however MIMO detection has huge amount of computations, which increases power consumption. To solve this, we propose a technique to reduce power consumption by introducting dynamic MIMO detection and dynamic voltage and frequency scaling (DVFS). Dynamic MIMO detection computes the weight matrix across multiple packets. A DVFS technique gives a dynamic operating voltage and frequnency to the MIMO detector circuit. This circuit has been implemented in to pipelined MMSE detector curciuts developed in our previous studies. We report the evaluation results in communication performance and power consumption.
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Keyword(in English) MIMO-OFDM / MIMO decoder / Low power consumption / DVFS
Paper # SIS2011-11
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Committee SIS
Conference Date 2011/6/2(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Power Reduction of MIMO-OFDM Receiver Circuits Using Dynamic MIMO Detection Techniques
Sub Title (in English)
Keyword(1) MIMO-OFDM
Keyword(2) MIMO decoder
Keyword(3) Low power consumption
Keyword(4) DVFS
1st Author's Name Nozomi MIYAZAKI
1st Author's Affiliation Graduate School of Information Science and Technology, Hokkaido University()
2nd Author's Name Shingo YOSHIZAWA
2nd Author's Affiliation Graduate School of Information Science and Technology, Hokkaido University
3rd Author's Name Yoshikazu MIYANAGA
3rd Author's Affiliation Graduate School of Information Science and Technology, Hokkaido University
Date 2011-06-09
Paper # SIS2011-11
Volume (vol) vol.111
Number (no) 78
Page pp.pp.-
#Pages 6
Date of Issue