Presentation 2011-06-30
Petri Net Based Task Scheduling for Dynamically Partially Reconfigurable FPGAs
Yuya SAKAI, Toshimitsu USHIO, Jun KOHJINA,
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Abstract(in English) FPGAs are integrated circuits intended for custom hardware implementation. They consist of programable components called configurable logic blocks(CLBs), which are arranged in a matrix pattern in FPGAs. Using the partial reconfigurable technology, a part of device executes a task while the other part is reconfigured. Recently, dynamically partially reconfigurable FPGAs become widely used. In order to use FPGAs effectively, it is important to schedule both execution of tasks and reconfigurations simultaneously. In this paper, we model both periodical tasks and a reconfigurable device with two-level hierarchical Petri nets. We propose a method for scheduling both tasks and reconfigurations without deadline miss.
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Keyword(in English) FPGA / two-level hierarchical Petri nets / Scheduling
Paper # CAS2011-6,VLD2011-13,SIP2011-35,MSS2011-6
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Committee SIP
Conference Date 2011/6/23(1days)
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Registration To Signal Processing (SIP)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Petri Net Based Task Scheduling for Dynamically Partially Reconfigurable FPGAs
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) two-level hierarchical Petri nets
Keyword(3) Scheduling
1st Author's Name Yuya SAKAI
1st Author's Affiliation Graduate School of Engineering Science, Osaka University()
2nd Author's Name Toshimitsu USHIO
2nd Author's Affiliation Graduate School of Engineering Science, Osaka University
3rd Author's Name Jun KOHJINA
3rd Author's Affiliation Graduate School of Engineering Science, Osaka University
Date 2011-06-30
Paper # CAS2011-6,VLD2011-13,SIP2011-35,MSS2011-6
Volume (vol) vol.111
Number (no) 104
Page pp.pp.-
#Pages 6
Date of Issue