Presentation | 2011-05-13 An Implementation of Programmable Re-Ordering Unit for Array Processor Tomoyoshi KOBORI, Nozomi ISHIHARA, Katsutoshi SEKI, Masao IKEKAWA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | We present a novel re-ordering unit architecture for array processor. In novel re-ordering unit, memory architecture is optimized with changing data re-ordering algorithm which uses smaller memories compared with traditional one, and unit control strategy that it makes several instruction memories to be integrated. Comparing with Re-ordering unit on CORSAEngine which we developed, the amount of memory is reduced about 30 %. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Array processor / wireless signal processing / data re-ordering / unit |
Paper # | RECONF2011-18 |
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Committee | RECONF |
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Conference Date | 2011/5/5(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Reconfigurable Systems (RECONF) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | An Implementation of Programmable Re-Ordering Unit for Array Processor |
Sub Title (in English) | |
Keyword(1) | Array processor |
Keyword(2) | wireless signal processing |
Keyword(3) | data re-ordering |
Keyword(4) | unit |
1st Author's Name | Tomoyoshi KOBORI |
1st Author's Affiliation | NEC Corporation() |
2nd Author's Name | Nozomi ISHIHARA |
2nd Author's Affiliation | NEC Corporation |
3rd Author's Name | Katsutoshi SEKI |
3rd Author's Affiliation | NEC Corporation |
4th Author's Name | Masao IKEKAWA |
4th Author's Affiliation | NEC Corporation |
Date | 2011-05-13 |
Paper # | RECONF2011-18 |
Volume (vol) | vol.111 |
Number (no) | 31 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |