| Presentation | 2011-05-13 Implementation and Evaluation of a low power accelerator SLD-2 Mai IZAWA, Nobuaki OZAKI, Yoshihiro YASUDA, Masayuki KIMURA, Hideharu AMANO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Silent Large Datapath or SLD is a novel high performance but low power accelerator architecture for battery driven mobile devices. The first prototype SLD-1 implemented with 65nm CMOS process is consisting with 8×8 PE array with pure combinatorial logic, a small μ-controller to keep flexibility of data management, and data memory. Although it achieved a high degree of energy efficiency, problems are found on I/O, mapping flexibility and the performance of the μ-controller. In order to improve the above problems, the second prototype SLD-2 with 10×8 PE array was implemented with 40nm CMOS process. By increasing the size of PE array and constant registers, the mapping flexibility of application programs was improved. Pipelined u controller a large instruction memory using the register file IP can work a higher clock generated from PLL. The evaluation result with real chip shows that it achieved 1.24 times energy efficiency of SLD-1. The maximum energy efficiency is 218MOPS/mW. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Reconfigurable System / Low Power Design / Implementation / Real Chip Evaluation |
| Paper # | RECONF2011-16 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2011/5/5(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Implementation and Evaluation of a low power accelerator SLD-2 |
| Sub Title (in English) | |
| Keyword(1) | Reconfigurable System |
| Keyword(2) | Low Power Design |
| Keyword(3) | Implementation |
| Keyword(4) | Real Chip Evaluation |
| 1st Author's Name | Mai IZAWA |
| 1st Author's Affiliation | Faculty of science and Technology, Keio University() |
| 2nd Author's Name | Nobuaki OZAKI |
| 2nd Author's Affiliation | Faculty of science and Technology, Keio University |
| 3rd Author's Name | Yoshihiro YASUDA |
| 3rd Author's Affiliation | Faculty of science and Technology, Keio University |
| 4th Author's Name | Masayuki KIMURA |
| 4th Author's Affiliation | Faculty of science and Technology, Keio University |
| 5th Author's Name | Hideharu AMANO |
| 5th Author's Affiliation | Faculty of science and Technology, Keio University |
| Date | 2011-05-13 |
| Paper # | RECONF2011-16 |
| Volume (vol) | vol.111 |
| Number (no) | 31 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |