Presentation 2011-05-13
Evaluation of Scalable Streaming Array for High-Performance Stencil Computation with Low Memory Bandwidth
Kentaro SANO, Yoshiaki HATSUDA, Yoshiaki KONO, Satoru YAMAMOTO,
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Abstract(in English) Stencil computation is one of the important kernels in scientific computations, however, the sustained performance is limited by memory bandwidth on multi-core processors and GPGPUs due to its small operational-intensity. In this paper, we propose a scalable streaming-array (SSA), which allows multiple FPGAs to achieve linearly-scalable stencil computation by deeply pipelining with a constant external-memory bandwidth. We present a design of SSA and formulate a performance model of the pipelined execution. For 2D Jacobi computations, SSA implemented on nine Stratix III FPGAs with the memory bandwidth of only 2 GB/s achieves 260 GFlop/s, corresponding to 87.4 % of the peak, due to the linear speedup obtained for larger than medium-sized computation.
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Keyword(in English) high-performance computation / stencil computation / scalable streaming-array / FPGA
Paper # RECONF2011-14
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Committee RECONF
Conference Date 2011/5/5(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) Evaluation of Scalable Streaming Array for High-Performance Stencil Computation with Low Memory Bandwidth
Sub Title (in English)
Keyword(1) high-performance computation
Keyword(2) stencil computation
Keyword(3) scalable streaming-array
Keyword(4) FPGA
1st Author's Name Kentaro SANO
1st Author's Affiliation Graduate School of Information Sciences, Tohoku University()
2nd Author's Name Yoshiaki HATSUDA
2nd Author's Affiliation Kobo Co. Ltd
3rd Author's Name Yoshiaki KONO
3rd Author's Affiliation Graduate School of Information Sciences, Tohoku University
4th Author's Name Satoru YAMAMOTO
4th Author's Affiliation Graduate School of Information Sciences, Tohoku University
Date 2011-05-13
Paper # RECONF2011-14
Volume (vol) vol.111
Number (no) 31
Page pp.pp.-
#Pages 6
Date of Issue