Presentation | 2011-05-12 Implementation of Bundled-Data Asynchronous Circuits on FPGA and thier Performance Evaluation Tadashi OKABE, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Asynchronous circuit design can solved many problems related to power consumption, EMI, clock skew and so on. Recently many researcheres and engineers are favolable interest in this design scheme. Also bundled-data design, a design style in various asynchronous circuit designs, has some advantages for efficinet use of IP cores and implementation about power saving, lower emission noise and high throughput processing. In this article, we present a connecting method and an interface block between synchronous circuit blocks and asynchronous circuit blocks. Furthermore we report asynchronous 4 phase bundled-data IP implementation on a FPGA, their performance evaluation and result of comparing asynchronous block with synchronous block. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Asynchronous circuit design / bundled-data style / FPGA / power saving |
Paper # | RECONF2011-7 |
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Conference Information | |
Committee | RECONF |
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Conference Date | 2011/5/5(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Reconfigurable Systems (RECONF) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Implementation of Bundled-Data Asynchronous Circuits on FPGA and thier Performance Evaluation |
Sub Title (in English) | |
Keyword(1) | Asynchronous circuit design |
Keyword(2) | bundled-data style |
Keyword(3) | FPGA |
Keyword(4) | power saving |
1st Author's Name | Tadashi OKABE |
1st Author's Affiliation | Tokyo Metlopolitan Industrial Technology Research Institute, Research and Development Department I() |
Date | 2011-05-12 |
Paper # | RECONF2011-7 |
Volume (vol) | vol.111 |
Number (no) | 31 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |