Presentation 2011-05-12
Pattern Compression of FAST Corner Detection and its FPGA Implementation
Keisuke DOHI, Yuji YORITA, Yuichiro SHIBATA, Kiyoshi OGURI,
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Abstract(in English) This paper shows stream-oriented FPGA implementation of the Features from Accelerated Segment Test (FAST) corner detection, which is used in the parallel tracking and mapping (PTAM) for augmented reality (AR). The matching process with a large number of corner patterns is one of the problems for implementing machine-learned FAST corner detection on an embedded hardware system like FPGAs. We propose compression methods of the corner patterns considering discriminant split and pattern symmetry for rotation and inversion. We proposed methods enable implementation of the machine-learned FAST corner detection with a combinational circuit. This implementation of the machine-learned FAST corner detection achieves real-time execution performance with 7-9% of available slices of a Virtex-5 FPGA.
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Keyword(in English) FAST Corner Detection / PTAM / FPGA / Pattern matching
Paper # RECONF2011-2
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Committee RECONF
Conference Date 2011/5/5(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Pattern Compression of FAST Corner Detection and its FPGA Implementation
Sub Title (in English)
Keyword(1) FAST Corner Detection
Keyword(2) PTAM
Keyword(3) FPGA
Keyword(4) Pattern matching
1st Author's Name Keisuke DOHI
1st Author's Affiliation Graduate School of Engineering, Nagasaki University()
2nd Author's Name Yuji YORITA
2nd Author's Affiliation School of Engineering, Nagasaki University
3rd Author's Name Yuichiro SHIBATA
3rd Author's Affiliation Graduate School of Engineering, Nagasaki University
4th Author's Name Kiyoshi OGURI
4th Author's Affiliation Graduate School of Engineering, Nagasaki University
Date 2011-05-12
Paper # RECONF2011-2
Volume (vol) vol.111
Number (no) 31
Page pp.pp.-
#Pages 6
Date of Issue