| Presentation | 2011-05-19 Super-resolution by Using Weighted Adders with Selector Logics Hiromine YOSHIHARA, Masao YANAGISAWA, Tatsuo OHTSUKI, Nozomu TOGAWA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In recent years the popularity of television sets and computers with large screens has let to more opportunities to watch moving picture on high-resolution liquid crystal display (LCD) where it is quite necessary to convert low-resolution images to high-resolution ones at low cost. Super-resolution is a technique to remove the noise of observed images and restore the high frequencise of ones. We focus on reconstruction-based super-resolution because it can restore their own brightnesses. It produces a high-resolution image from a set of low-resolution images. Reconstruction requires large computation cost because it requires many images. However, it is necessary to improve arithmetic circuits' performance specific to reconstruction-based super-resolution since the reconstruction-based algorithms need more information on images. In this paper, we propose a reconstruction-based super-resolution using a weighted adder. Our weighted adder is implemented by using selector logics so that we can reduce carry propagations and improve the performance of reconstruction-based super-resolution. Finally, experimental results demonstrate that our proposed weighted adder circuit improves the performance by 13 % and reduces the area by 32 %, compared to conventional weighted adders. |
| Keyword(in Japanese) | (See Japanese page) |
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| Paper # | VLD2011-6 |
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| Committee | VLD |
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| Conference Date | 2011/5/11(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Super-resolution by Using Weighted Adders with Selector Logics |
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| 1st Author's Name | Hiromine YOSHIHARA |
| 1st Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University() |
| 2nd Author's Name | Masao YANAGISAWA |
| 2nd Author's Affiliation | Dept. of Electronic and Photonic Systems, Waseda University |
| 3rd Author's Name | Tatsuo OHTSUKI |
| 3rd Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| 4th Author's Name | Nozomu TOGAWA |
| 4th Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| Date | 2011-05-19 |
| Paper # | VLD2011-6 |
| Volume (vol) | vol.111 |
| Number (no) | 40 |
| Page | pp.pp.- |
| #Pages | 6 |
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