| Presentation | 2011-04-22 Decoupling of Power Distribution Network to Improve Tolerance of Side-Channel Attacks in Cryptographic FPGA Tetsuo AMANO, Kengo IOKIBE, Yoshitaka TOYOTA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Side-channel attack is a cryptanalytic attack by means of radio frequency (RF) power current from cryptographic IC. On-board decoupling was examined experimentally in two decoupling conditions and the default no-decoupling condition to prove its usefulness as a countermeasure against the side-channel attack. The RF power current of a cryptographic FPGA (Field-Programmable Gate Array) was decoupled with a decoupling circuit. The decoupling circuit was installed in the power distribution network of the cryptographic FPGA on a Side-channel attack standard evaluation baord, SASEBO-G. The RF power current which was generated as the FPGA was operating an AES (Advanced Encryption Standard) encryption process was detected with a current probe on power cables. The current detection was repeated until 30,000 waveforms were obtained in each decoupling conditions. The waveforms were analyzed statistically by the correlation power analysis (CPA). CPA results showed that one of the decoupling circuits improved tolerance of the FPGA to the side-channel attack, while the other decoupling circuit hardly change the tolerance. Noticeable difference between the two decoupling circuits appeared in the frequency range below the frequency of the FPGA clock. The RF power current was reduced all over the lower range in the decoupling condition the tolerance improved. The RF power current reduction was proved to be a result of the decoupling by circuit simulations. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Cryptograph / Side-channel attacks / Decoupling capacitor / Decoupling inductor / AES / CPA |
| Paper # | EMCJ2011-4 |
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| Conference Information | |
| Committee | EMCJ |
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| Conference Date | 2011/4/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Electromagnetic Compatibility (EMCJ) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Decoupling of Power Distribution Network to Improve Tolerance of Side-Channel Attacks in Cryptographic FPGA |
| Sub Title (in English) | |
| Keyword(1) | Cryptograph |
| Keyword(2) | Side-channel attacks |
| Keyword(3) | Decoupling capacitor |
| Keyword(4) | Decoupling inductor |
| Keyword(5) | AES |
| Keyword(6) | CPA |
| 1st Author's Name | Tetsuo AMANO |
| 1st Author's Affiliation | Graduate School of Natural Science and Technology, Okayama University() |
| 2nd Author's Name | Kengo IOKIBE |
| 2nd Author's Affiliation | Graduate School of Natural Science and Technology, Okayama University |
| 3rd Author's Name | Yoshitaka TOYOTA |
| 3rd Author's Affiliation | Graduate School of Natural Science and Technology, Okayama University |
| Date | 2011-04-22 |
| Paper # | EMCJ2011-4 |
| Volume (vol) | vol.111 |
| Number (no) | 18 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |