Presentation	2011-03-03 An FPGA-based fast classifier with high generalization property Tadayoshi HORITA, Itsuo TAKANAMI,
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Abstract(in English)	This paper proposes a scheme to implement classifiers with high generalization properties on FPGAs. The classifiers consist of only combinational logic circuits, which are based on a simple concept, and the VHDL source files which describe the classifiers are generated by a C-language function, tuning VHDL notations for adders in them to reduce both its hardware size and computation time. Simulation results based on a character recognition are shown in terms of generalization property, hardware size, computation time, and electricity consumption.
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Keyword(in English)	classifier / FPGA / generalization property / VHDL / tuned code generation
Paper #	SIS2010-54
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Committee	SIS
Conference Date	2011/2/24(1days)
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Registration To	Smart Info-Media Systems (SIS)
Language	ENG
Title (in Japanese)	(See Japanese page)
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Title (in English)	An FPGA-based fast classifier with high generalization property
Sub Title (in English)
Keyword(1)	classifier
Keyword(2)	FPGA
Keyword(3)	generalization property
Keyword(4)	VHDL
Keyword(5)	tuned code generation
1st Author's Name	Tadayoshi HORITA
1st Author's Affiliation	Politechnic Univercity /()
2nd Author's Name	Itsuo TAKANAMI
2nd Author's Affiliation
Date	2011-03-03
Paper #	SIS2010-54
Volume (vol)	vol.110
Number (no)	445
Page	pp.pp.-
#Pages	6
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