| Presentation | 2011-04-12 Note on Defect Level Evaluation of Cascaded TMR for Pipeline Processors Masayuki Arai, Kazuhiko Iwasaki, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this study we evaluate effectiveness of cascaded triple modular redundancy (TMR) where TMR is applied to every stage of a pipeline processor, in respect to area per a good chip and defect level. For two different TMR arrangements, we theoretically derive area per a good chip based on given defect density and the number of stages. Also, assuming that production test is applied for each module and voter in every stage independently and that pass/fail of a chip is determined based on the test result, we theoretically derive defect level for given fault coverage. Numerical examples show that application of cascaded TMR improves area per a good chip and defect level in the case where manufactiiring yield is low, and also that there are some cases where the number of stages which minimizes area per a good chip or defect level exists. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | cascaded TMR / defect level / test escape / area per a good chip |
| Paper # | CPSY2011-6,DC2011-6 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2011/4/5(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Note on Defect Level Evaluation of Cascaded TMR for Pipeline Processors |
| Sub Title (in English) | |
| Keyword(1) | cascaded TMR |
| Keyword(2) | defect level |
| Keyword(3) | test escape |
| Keyword(4) | area per a good chip |
| 1st Author's Name | Masayuki Arai |
| 1st Author's Affiliation | Faculty of System Design, Tokyo Metropolitan University() |
| 2nd Author's Name | Kazuhiko Iwasaki |
| 2nd Author's Affiliation | Faculty of System Design, Tokyo Metropolitan University |
| Date | 2011-04-12 |
| Paper # | CPSY2011-6,DC2011-6 |
| Volume (vol) | vol.111 |
| Number (no) | 2 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |