Presentation 2011-04-12
Transient-Fault-Tolerant Out-of-Order Superscalar Processor
Satoshi ARIMA, Takashi OKADA, Ryota SHIOYA, Masahiro GOSHIMA, Shuichi SAKAI,
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Abstract(in English) Recently, LSI is shrinking and random-variability problem is increasing. For further growth of semiconductor industry, circuit techniques which relax restrictions from variability is required. One of existing techniques for processors is using timing-fault(TF) tolerancy. In this reserch, we propose a TF correction method using Pipeline Initialization and a commit scheme based on our new concept which is named Commit Pipeline. This proposal realizes TF tolerant out-of-order superscalar processors.
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Keyword(in English) variability / timing fault / commit / reorder buffer / load/store queue
Paper # CPSY2011-5,DC2011-5
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Committee DC
Conference Date 2011/4/5(1days)
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Paper Information
Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Transient-Fault-Tolerant Out-of-Order Superscalar Processor
Sub Title (in English)
Keyword(1) variability
Keyword(2) timing fault
Keyword(3) commit
Keyword(4) reorder buffer
Keyword(5) load/store queue
1st Author's Name Satoshi ARIMA
1st Author's Affiliation Dept. of Information and Communication Eng, the Univ. of Tokyo()
2nd Author's Name Takashi OKADA
2nd Author's Affiliation Dept. of Information and Communication Eng, the Univ. of Tokyo
3rd Author's Name Ryota SHIOYA
3rd Author's Affiliation Dept. of Information and Communication Eng, the Univ. of Tokyo:Young Scientists DC
4th Author's Name Masahiro GOSHIMA
4th Author's Affiliation Dept. of Information and Communication Eng, the Univ. of Tokyo
5th Author's Name Shuichi SAKAI
5th Author's Affiliation Dept. of Information and Communication Eng, the Univ. of Tokyo
Date 2011-04-12
Paper # CPSY2011-5,DC2011-5
Volume (vol) vol.111
Number (no) 2
Page pp.pp.-
#Pages 6
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