Presentation 2011-04-12
Tamper LSI Design Methodology Resistant to Malicious Attack
Takeshi FUJINO, Mitsuru SHIOZAKI, Masaya Yoshikawa,
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Abstract(in English) Tamper LSI Design Methodology have to be applied in order to implement secure cryptographic circuit which is resistant to side-channel attack such as DPA (Differential Power Analysis). The principle of DPA and some typical countermeasures against DPA are introduced and discussed the problem on the LSI implementation. The domino-RSL technique, which randomizes the output transition rate by the random number, is easy to implement in the conventional LSI design flow. The DES cryptographic circuit was designed by this technique, and a good DPA resistance is demonstrated on the test chip.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Tamper Resistant LSI / Side-Channel Attack / DPA / CPA / WDDL / RSL / Domino-RSL
Paper # CPSY2011-4,DC2011-4
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Committee DC
Conference Date 2011/4/5(1days)
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Paper Information
Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Tamper LSI Design Methodology Resistant to Malicious Attack
Sub Title (in English)
Keyword(1) Tamper Resistant LSI
Keyword(2) Side-Channel Attack
Keyword(3) DPA
Keyword(4) CPA
Keyword(5) WDDL
Keyword(6) RSL
Keyword(7) Domino-RSL
1st Author's Name Takeshi FUJINO
1st Author's Affiliation Faculty of Science and Engineering, Ritsumeikan University()
2nd Author's Name Mitsuru SHIOZAKI
2nd Author's Affiliation Research Organization of Science and Engineering, Ritsumeikan University
3rd Author's Name Masaya Yoshikawa
3rd Author's Affiliation Faculty of Science and Engineering, Meijo University
Date 2011-04-12
Paper # CPSY2011-4,DC2011-4
Volume (vol) vol.111
Number (no) 2
Page pp.pp.-
#Pages 6
Date of Issue