Presentation 2011-03-19
An Architecture for Low-Latency Anonymizing Mechanism
Junichi SAWADA, Koichi INOUE, Hiroaki NISHI,
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Abstract(in English) In experiencing the growth of quantity and value of data, data holders realize the importance to utilize information that is abandoned or concealed currently. In this situation, they face the difficulty of releasing data without revealing privacy information. One of the methods to protect privacy information in publishing data is known as a privacy preserving method based on a constraint termed k-anonymity and i-diversity. It enables users of the data to utilize published data as they like. However, it requires a large running time. This research proposes TCAM-based hardware architecture for accelerating k-anonymity and i-diversity algorithm and improves its performance. The evaluation on FPGA device proves that the proposed architecture achieves approximately 10-50 times faster throughput than a RAM-based architecture.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Hardware / Data Privacy / Privacy-Preserving Data Publishing / k-anonymity / l-diversity
Paper # CPSY2010-81,DC2010-80
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Committee DC
Conference Date 2011/3/11(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An Architecture for Low-Latency Anonymizing Mechanism
Sub Title (in English)
Keyword(1) Hardware
Keyword(2) Data Privacy
Keyword(3) Privacy-Preserving Data Publishing
Keyword(4) k-anonymity
Keyword(5) l-diversity
1st Author's Name Junichi SAWADA
1st Author's Affiliation Faculty of Science and Technology, Keio University()
2nd Author's Name Koichi INOUE
2nd Author's Affiliation Graduate School of Science and Technology, Keio University
3rd Author's Name Hiroaki NISHI
3rd Author's Affiliation Graduate School of Science and Technology, Keio University
Date 2011-03-19
Paper # CPSY2010-81,DC2010-80
Volume (vol) vol.110
Number (no) 474
Page pp.pp.-
#Pages 6
Date of Issue