Presentation 2011-03-19
Virtual HILS : Efficient software validation by entire system virtualization
Yasuhiro ITO, Yasuo SUGURE, Shigeru OHO,
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Abstract(in English) VHILS, a system simulation environment for validating dependability of embedded systems was developed. VHILS is equiped with general purpose simulation interface which speeds up communication between mechanical simulation and electoric one. By using the interface, VHILS could achieve 43% speed compare to that of the acutual system component with 0.1% error at most. VHILS could overcome time and resource limitations of control-system validation by exploiting its feature, VHILS was formed only by software. A computer system that proves automation and parallelization of system validation was developed.
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Keyword(in English) VHILS / System Simulation / CPU Emulation
Paper # CPSY2010-76,DC2010-75
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Committee DC
Conference Date 2011/3/11(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Virtual HILS : Efficient software validation by entire system virtualization
Sub Title (in English)
Keyword(1) VHILS
Keyword(2) System Simulation
Keyword(3) CPU Emulation
1st Author's Name Yasuhiro ITO
1st Author's Affiliation Hitachi, Ltd. Central Research Laboratory()
2nd Author's Name Yasuo SUGURE
2nd Author's Affiliation Hitachi, Ltd. Central Research Laboratory
3rd Author's Name Shigeru OHO
3rd Author's Affiliation Hitachi, Ltd. Central Research Laboratory
Date 2011-03-19
Paper # CPSY2010-76,DC2010-75
Volume (vol) vol.110
Number (no) 474
Page pp.pp.-
#Pages 5
Date of Issue