Presentation | 2011-03-18 Design Method of Easily Testable Parallel Adders under Delay Constraints Shinichi FUJII, Naofumi TAKAGI, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | The design of easily testable arithmetic circuits is important. A lot of design methods of adders, considering performance requirements such as circuit delay and area constraints, have been proposed. In this paper, we propose a design method of easily testable adders under delay constraints. We propose a design method of easily testable carry select adder and a parallel prefix adder designed under trade-off of delay and the number of test patterns. We propose a design method of a adder with fewer test patterns by selecting an adder construction according to delay constraints. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | carry select adder / parallel prefix adders / design for testability |
Paper # | CPSY2010-75,DC2010-74 |
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Committee | DC |
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Conference Date | 2011/3/11(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Dependable Computing (DC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Design Method of Easily Testable Parallel Adders under Delay Constraints |
Sub Title (in English) | |
Keyword(1) | carry select adder |
Keyword(2) | parallel prefix adders |
Keyword(3) | design for testability |
1st Author's Name | Shinichi FUJII |
1st Author's Affiliation | Department of Information Enginnering, Nagoya University() |
2nd Author's Name | Naofumi TAKAGI |
2nd Author's Affiliation | Department of Comunications and Computer Engineering, Graduate School of Informatics, Kyoto University |
Date | 2011-03-18 |
Paper # | CPSY2010-75,DC2010-74 |
Volume (vol) | vol.110 |
Number (no) | 474 |
Page | pp.pp.- |
#Pages | 6 |
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