| Presentation | 2011-02-14 A Test Generation Method for Datapath Circuits Using Functional Time Expansion Models Teppei HAYAKAWA, Toshinori HOSOKAWA, Masayoshi YOSHIMURA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Some large-scale integrated circuits have been recently designed at high-level by behavioral descriptions. Behavioral synthesis can transform behavioral descriptions to register transfer level circuits that consist of a controller and a datapath. In this paper, we propose a test generation method for datapath circuits using functional time expansion models which are defmed as time expansion models with functional information such as latency, and the input sequence for control signal lines and the output sequence for status signal lines of datapaths. We also propose two types of functional time expansion model generation methods. One is generated from controllers and the other is generated from functional verification patterns. Experimental results for practical circuits show that the proposed test generation methods increase fault coverage by 14.98% on the average and accelerate test generation time by 81.29 times on the average |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | n-state transition cover / functional time expansion models / datapath circuits / constrained sequential test generation |
| Paper # | DC2010-65 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2011/2/7(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Test Generation Method for Datapath Circuits Using Functional Time Expansion Models |
| Sub Title (in English) | |
| Keyword(1) | n-state transition cover |
| Keyword(2) | functional time expansion models |
| Keyword(3) | datapath circuits |
| Keyword(4) | constrained sequential test generation |
| 1st Author's Name | Teppei HAYAKAWA |
| 1st Author's Affiliation | Graduate School of Industrial Technology, Nihon University() |
| 2nd Author's Name | Toshinori HOSOKAWA |
| 2nd Author's Affiliation | College of Industrial Technology, Nihon University |
| 3rd Author's Name | Masayoshi YOSHIMURA |
| 3rd Author's Affiliation | Faculty of Engineering, Kyushu University |
| Date | 2011-02-14 |
| Paper # | DC2010-65 |
| Volume (vol) | vol.110 |
| Number (no) | 413 |
| Page | pp.pp.- |
| #Pages | 6 |
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