| Presentation | 2011/3/11 Low-speed Detection by a Fail-safe Counter Sansak DEEON, Yuji HIRAO, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A low-speed detection method using a fail-safe counter is proposed. Specific features of this proposed method are, firstly, the adoption of digital counter circuits for detection of low-speed, and, secondly, the diagnosis of the digital counter circuit and its result output as dynamic signals to a band-pass filter and a charge pump circuit with a window comparator. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Fail-safe / Failure modes and effects analysis (FMEA) / Low-speed detection / Safety devices |
| Paper # | SSS2010-27 |
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| Conference Information | |
| Committee | SSS |
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| Conference Date | 2011/3/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Safety (SSS) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Low-speed Detection by a Fail-safe Counter |
| Sub Title (in English) | |
| Keyword(1) | Fail-safe |
| Keyword(2) | Failure modes and effects analysis (FMEA) |
| Keyword(3) | Low-speed detection |
| Keyword(4) | Safety devices |
| 1st Author's Name | Sansak DEEON |
| 1st Author's Affiliation | Nagaoka University of Technology() |
| 2nd Author's Name | Yuji HIRAO |
| 2nd Author's Affiliation | Nagaoka University of Technology |
| Date | 2011/3/11 |
| Paper # | SSS2010-27 |
| Volume (vol) | vol.110 |
| Number (no) | 472 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |