Presentation 2011-01-24
Stochastic Resonance in Subthreshold Logic Memory Circuit
Akira UTAGAWA, Kazunori YOSHIDA, Tetsuya ASAI, Yoshihito AMEMIYA,
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Abstract(in English) We demonstrate stochastic resonance (SR) in a logic memory circuit operating in the subthreshold region. In previous report, we proposed double-well potential system that could easily be implemented by a single OP-AMP and demonstrated stochastic resonance in electrical experiments with simple circuit construction. In this report, we implemented the system by employing a OTA with five transistors to investigate a possible noise-driven logic memory circuit operating in the subthreshold region. We examined SR behaviors in circuit simulations. By applying moderate noises to the system, the circuit could stochastically detect the input and the internal state changed correctly. By calculating failure rate of the memory cells, we found that the system exhibited the same SR behaviors as in the previous circuit. The power consumption of the proposed circuit was 150 pW, whereas the power consumption of a conventional logic memory circuit composed of two inverter circuits was 14.6 nW. Finally, we investigated the effect of decreasing the supply voltage of the circuit to reduce power consumption further. When Vdd was set to 0.5 V, power consumption of the proposed circuit was lower than that of the latch circuit by 30%.
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Keyword(in English) stochastic resonance / double-well potential / electrical circuits
Paper # NLP2010-131,NC2010-95
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Conference Information
Committee NC
Conference Date 2011/1/17(1days)
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Paper Information
Registration To Neurocomputing (NC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Stochastic Resonance in Subthreshold Logic Memory Circuit
Sub Title (in English)
Keyword(1) stochastic resonance
Keyword(2) double-well potential
Keyword(3) electrical circuits
1st Author's Name Akira UTAGAWA
1st Author's Affiliation Graduate School of Information Science and Technology, Hokkaido University()
2nd Author's Name Kazunori YOSHIDA
2nd Author's Affiliation Graduate School of Information Science and Technology, Hokkaido University
3rd Author's Name Tetsuya ASAI
3rd Author's Affiliation Graduate School of Information Science and Technology, Hokkaido University
4th Author's Name Yoshihito AMEMIYA
4th Author's Affiliation Graduate School of Information Science and Technology, Hokkaido University
Date 2011-01-24
Paper # NLP2010-131,NC2010-95
Volume (vol) vol.110
Number (no) 388
Page pp.pp.-
#Pages 6
Date of Issue