Presentation 2010-12-17
Comparison of the Error Correction Methods for SSDs and Dynamic Codeword Transition ECC Scheme
Shuhei TANAKAMARU, Atsushi ESUMI, Mitsuyoshi ITO, Kai LI, Ken TAKEUCHI,
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Abstract(in English) This paper compares error correcting codes (ECC) such as RS code and BCH code as an ECC for SSDs and introduces dynamic codeword transition ECC scheme for highly reliable SSDs. By monitoring the error number or the write / erase cycles, the ECC codeword dynamically increases from 512Byte (+parity) to 1KByte, 2KByte, 4KByte...32KByte. The proposed ECC with a larger codeword decreases the failure rate after ECC. Because the parity rate per codeword is the same in each ECC codeword, no additional memory area is required so that the reliability of SSD is improved after the manufacturing without cost penalty.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) ECC / Error correcting code / SSD / NAND Flash memory
Paper # ICD2010-124
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Committee ICD
Conference Date 2010/12/9(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Comparison of the Error Correction Methods for SSDs and Dynamic Codeword Transition ECC Scheme
Sub Title (in English)
Keyword(1) ECC
Keyword(2) Error correcting code
Keyword(3) SSD
Keyword(4) NAND Flash memory
1st Author's Name Shuhei TANAKAMARU
1st Author's Affiliation Dept. of Electrical Engineering and Information Systems, University of Tokyo()
2nd Author's Name Atsushi ESUMI
2nd Author's Affiliation SIGLEAD Inc.
3rd Author's Name Mitsuyoshi ITO
3rd Author's Affiliation SIGLEAD Inc.
4th Author's Name Kai LI
4th Author's Affiliation SIGLEAD Inc.
5th Author's Name Ken TAKEUCHI
5th Author's Affiliation Dept. of Electrical Engineering and Information Systems, University of Tokyo
Date 2010-12-17
Paper # ICD2010-124
Volume (vol) vol.110
Number (no) 344
Page pp.pp.-
#Pages 6
Date of Issue