Presentation 2010-12-16
Evaluation of power noise in SRAM core
Taku Toshikawa, Tsubasa Masui, Takuya Sawada, Makoto Nagata,
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Abstract(in English) Power noise of SRAM operation is evaluated with a test chip fabricated in a 90-nm CMOS technology. The chip includes on-die voltage monitors, BIST structures for failure bit detection and analysis, and a set of SRAM macros with different bit and word specifications. Power and ground noise waveforms are measured and compared in a variety of operation conditions in both user and BIST modes. It is found that power noise depends on an operating frequency of memory, in terms of their average and amplitudes. We are challenging to relate power noise and bit failures, by using automatic measurement systems of power noise, bit error rate, and fail bit map.
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Keyword(in English) SRAM / Power noise / on-die voltage monitor
Paper # ICD2010-112
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Committee ICD
Conference Date 2010/12/9(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Evaluation of power noise in SRAM core
Sub Title (in English)
Keyword(1) SRAM
Keyword(2) Power noise
Keyword(3) on-die voltage monitor
1st Author's Name Taku Toshikawa
1st Author's Affiliation Dept. of System Science , Kobe Univercity()
2nd Author's Name Tsubasa Masui
2nd Author's Affiliation Dept. of System Science , Kobe Univercity
3rd Author's Name Takuya Sawada
3rd Author's Affiliation Dept. of System Science , Kobe Univercity
4th Author's Name Makoto Nagata
4th Author's Affiliation Dept. of System Science , Kobe Univercity
Date 2010-12-16
Paper # ICD2010-112
Volume (vol) vol.110
Number (no) 344
Page pp.pp.-
#Pages 4
Date of Issue