Presentation 2010-12-16
Evaluation of Power Gating Structures Focusing on Power Supply Noise with Measurement and Simulation
Yasumichi TAKAI, Masanori HASHIMOTO, Takao ONOYE,
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Abstract(in English) This paper investigates the impact of power gating structure on power supply noise using 65nm test chip measurement and simulation. We focus on the body connection of power-gated circuits, and examine the contribution of a power-gated circuit as a decoupling capacitance during the sleep mode. Experimental results show that the well junction capacitance of the power-gated circuit with body-tied structure helps reduce power supply noise while a sharp drop cannot be mitigated due to its large RC time constant.
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Keyword(in English) on-chip power supply noise / power gating / well structure
Paper # ICD2010-109
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Conference Date 2010/12/9(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Evaluation of Power Gating Structures Focusing on Power Supply Noise with Measurement and Simulation
Sub Title (in English)
Keyword(1) on-chip power supply noise
Keyword(2) power gating
Keyword(3) well structure
1st Author's Name Yasumichi TAKAI
1st Author's Affiliation Graduate School of Information Science and Technology, Osaka University()
2nd Author's Name Masanori HASHIMOTO
2nd Author's Affiliation Graduate School of Information Science and Technology, Osaka University
3rd Author's Name Takao ONOYE
3rd Author's Affiliation Graduate School of Information Science and Technology, Osaka University
Date 2010-12-16
Paper # ICD2010-109
Volume (vol) vol.110
Number (no) 344
Page pp.pp.-
#Pages 6
Date of Issue