Presentation 2010-12-16
Chip Development of a Ubiquitous Processor
Harunobu UCHIUMI, Takumi ISHIHARA, Naomichi MIMURA, Kazuki NARITA, Tatsuya TAKAKI, Masa-aki FUKASE, Tomoaki SATO,
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Abstract(in English) The purpose of this study is the practical implementation of a ubiquitous processor Hcgorilla. This has a double core and multiple pipeline structure. The pipelines are Java compatible media pipes and hardware cipher bulit-in pipes. This paper describes to improve Hcgorilla by merging clock schemes for DFT and power saving. In addition, wave-pipelining is introduced to achieve higer throughput. Finally, the optimum design by using a 0.18-μm CMOS standard cell chip is evaluated.
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Keyword(in English) CMOS / standard cell / chip / ubiquitous processor
Paper # ICD2010-102
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Committee ICD
Conference Date 2010/12/9(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Chip Development of a Ubiquitous Processor
Sub Title (in English)
Keyword(1) CMOS
Keyword(2) standard cell
Keyword(3) chip
Keyword(4) ubiquitous processor
1st Author's Name Harunobu UCHIUMI
1st Author's Affiliation Faculty of Science and Technology, Hirosaki University()
2nd Author's Name Takumi ISHIHARA
2nd Author's Affiliation Faculty of Science and Technology, Hirosaki University
3rd Author's Name Naomichi MIMURA
3rd Author's Affiliation Faculty of Science and Technology, Hirosaki University
4th Author's Name Kazuki NARITA
4th Author's Affiliation Faculty of Science and Technology, Hirosaki University
5th Author's Name Tatsuya TAKAKI
5th Author's Affiliation Faculty of Science and Technology, Hirosaki University
6th Author's Name Masa-aki FUKASE
6th Author's Affiliation Faculty of Science and Technology, Hirosaki University
7th Author's Name Tomoaki SATO
7th Author's Affiliation C&C Systems Center, Hirosaki University
Date 2010-12-16
Paper # ICD2010-102
Volume (vol) vol.110
Number (no) 344
Page pp.pp.-
#Pages 6
Date of Issue