Presentation 2010-12-16
CMOS-Based Nonvolatile Flip-Flop Design and its Application to a Fractional-N PLL Frequency Synthesizer
Ge WANG, Jungyu LEE, Shoichi MASUI,
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Abstract(in English) A CMOS-based nonvolatile flip-flop (NV FF) is proposed and implemented with a 180nm technology without any additional masks. This NV FF is applied to a fractional-N phase-locked loop (PLL) frequency synthesizer for a smart key application for the output band selection and compensation of process variations in MOS capacitors. The additional pre-tuning of voltage-controlled oscillator (VCO) control voltage is executed with the combination of digital-to-analog converter (DAC) and NV FF for the fast start-up and resulting low-energy operation.
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Keyword(in English) Nonvolatile memory / Analog circuit calibration / Fractional-N PLL frequency synthesizer / low energy
Paper # ICD2010-100
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Committee ICD
Conference Date 2010/12/9(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) CMOS-Based Nonvolatile Flip-Flop Design and its Application to a Fractional-N PLL Frequency Synthesizer
Sub Title (in English)
Keyword(1) Nonvolatile memory
Keyword(2) Analog circuit calibration
Keyword(3) Fractional-N PLL frequency synthesizer
Keyword(4) low energy
1st Author's Name Ge WANG
1st Author's Affiliation Tohoku University()
2nd Author's Name Jungyu LEE
2nd Author's Affiliation Tohoku University
3rd Author's Name Shoichi MASUI
3rd Author's Affiliation Tohoku University
Date 2010-12-16
Paper # ICD2010-100
Volume (vol) vol.110
Number (no) 344
Page pp.pp.-
#Pages 6
Date of Issue