| Presentation | 2010-12-02 Circuit Design of a 128-point FFT Processor Using Pipeline MDC Architecture for 8x8 MIMO-OFDM Receivers Atsushi ORIKASA, Yoshikazu MIYANAGA, Shingo YOSHIZAWA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This report presents a VLSI architecture of 128-point FFT in a 8x8 MIMO-OFDM receiver. A pipeline FFT processor based on multi-path delay commutator(MDC) architecture is effective for 4x4 MIMO-OFDM systems. To achieve the communication of more high speed and large capacity, it is necessary to design the FFT processor corresponding to the MIMO-OFDM receiver that increases the number of streams. In this paper, we propose the FFT processor to apply the MDC architecture for 8x8 MIMO-OFDM systems. The proposed FFT processor uses the pre- and post-commutators instead of delay elements and improves area and power efficiency. The designed circuit has been implemented to a 90-nm CMOS process and evaluated in circuit area and power consumption. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FFT / Multi-path delay commutator(MDC) / MIMO-OFDM / VLSI Architecture |
| Paper # | SIS2010-45 |
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| Conference Information | |
| Committee | SIS |
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| Conference Date | 2010/11/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Smart Info-Media Systems (SIS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Circuit Design of a 128-point FFT Processor Using Pipeline MDC Architecture for 8x8 MIMO-OFDM Receivers |
| Sub Title (in English) | |
| Keyword(1) | FFT |
| Keyword(2) | Multi-path delay commutator(MDC) |
| Keyword(3) | MIMO-OFDM |
| Keyword(4) | VLSI Architecture |
| 1st Author's Name | Atsushi ORIKASA |
| 1st Author's Affiliation | Graduate School of Information Science and Technology, Hokkaido University() |
| 2nd Author's Name | Yoshikazu MIYANAGA |
| 2nd Author's Affiliation | Graduate School of Information Science and Technology, Hokkaido University |
| 3rd Author's Name | Shingo YOSHIZAWA |
| 3rd Author's Affiliation | Graduate School of Information Science and Technology, Hokkaido University |
| Date | 2010-12-02 |
| Paper # | SIS2010-45 |
| Volume (vol) | vol.110 |
| Number (no) | 322 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |