| Presentation | 2010-12-10 Research of Highly Reliable Fail-safe CPU Yasuo OGAWA, Akihisa ASAMI, Hideo NAKAMURA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | To defend from one breakdown of parts, three CPU was installed in FPGA. This method achieves the improvement of reliability, and it has the same stuff as fail-safe. The technique that was able to be switched internally when one of the three CPU broke down was developed. In this research paper, we explain the basic configuration and the fundamental motion. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | High-Reliablity / Fail-safe / CPU |
| Paper # | DC2010-56 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2010/12/3(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Research of Highly Reliable Fail-safe CPU |
| Sub Title (in English) | |
| Keyword(1) | High-Reliablity |
| Keyword(2) | Fail-safe |
| Keyword(3) | CPU |
| 1st Author's Name | Yasuo OGAWA |
| 1st Author's Affiliation | The Nippon Signal CO., LTD.() |
| 2nd Author's Name | Akihisa ASAMI |
| 2nd Author's Affiliation | The Nippon Signal CO., LTD. |
| 3rd Author's Name | Hideo NAKAMURA |
| 3rd Author's Affiliation | College of Science and Technology, The Nihon University |
| Date | 2010-12-10 |
| Paper # | DC2010-56 |
| Volume (vol) | vol.110 |
| Number (no) | 333 |
| Page | pp.pp.- |
| #Pages | 5 |
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