Presentation 2011-01-17
Power reduction in Dynamically Reconfigurable Processor by Dynamically V_
Switching and a mapping technique to reduce energy overhead
Tatsuya Yamamoto, Kazuei Hironaka, Yuki Hayakawa, Masayuki Kimura, Hideharu Amano, Kimiyoshi Usami,
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Abstract(in English) This paper describes a dynamic VDD switching technique to reduce energy dissipation of Dynamically Reconfigurable Processors. Either high or low supply is dynamically selected at each PE at the context-by-context basis. We designed a part of a PE array and applied this technique. A test chip fabricated in 65nm technology operated successfully. Detailed simulations revealed that energy reduction is hindered by energy overhead due to supply switching when we use even lower VDD. We propose a mapping optimization algorithm "PFCM" to minimize the overhead. PFCM reduced energy overhead by 87% and thereby the dynamic VDD switching technique reduced energy dissipation by up to 12%.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Dynamically Reconfigurable Processor / Power Reduction / Dynamic V_
Swiching / Mapping Optimization
Paper # VLD2010-92,CPSY2010-47,RECONF2010-61
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Committee RECONF
Conference Date 2011/1/10(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Power reduction in Dynamically Reconfigurable Processor by Dynamically V_
Switching and a mapping technique to reduce energy overhead
Sub Title (in English)
Keyword(1) Dynamically Reconfigurable Processor
Keyword(2) Power Reduction
Keyword(3) Dynamic V_
Swiching
Keyword(4) Mapping Optimization
1st Author's Name Tatsuya Yamamoto
1st Author's Affiliation Graduate School of Engineering, Shibaura Institute of Technology()
2nd Author's Name Kazuei Hironaka
2nd Author's Affiliation Graduate School of Science and Technology, Keio University
3rd Author's Name Yuki Hayakawa
3rd Author's Affiliation Graduate School of Engineering, Shibaura Institute of Technology
4th Author's Name Masayuki Kimura
4th Author's Affiliation Graduate School of Science and Technology, Keio University
5th Author's Name Hideharu Amano
5th Author's Affiliation Graduate School of Science and Technology, Keio University
6th Author's Name Kimiyoshi Usami
6th Author's Affiliation Graduate School of Engineering, Shibaura Institute of Technology
Date 2011-01-17
Paper # VLD2010-92,CPSY2010-47,RECONF2010-61
Volume (vol) vol.110
Number (no) 362
Page pp.pp.-
#Pages 6
Date of Issue