Presentation 2011-01-17
Parallelization of the channel width search for FPGA routing
Hiroomi SAWADA, Morihiro KUGA, Toshinori SUEYOSHI,
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Abstract(in English) As the FPGA becomes resourceful, the design time becomes longer. Especially, routing process occupies the large portion of it, because the routing patterns increase substantially with FPGA's growing. Therefore, we propose the parallelizing algorithm for FPGA's channel width search in order to reduce the automated design time. This algorithm doesn't lose the routing cost, because each channel width search are independent with respect to one another. As a result, we achieved speed-up 5.39 times highest, 1.90 times the rate improvement on the average without cost deterioration. cost deterioration.
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Keyword(in English) FPGA routing / parallel algorithm / cluster computer
Paper # VLD2010-89,CPSY2010-44,RECONF2010-58
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Committee RECONF
Conference Date 2011/1/10(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Parallelization of the channel width search for FPGA routing
Sub Title (in English)
Keyword(1) FPGA routing
Keyword(2) parallel algorithm
Keyword(3) cluster computer
1st Author's Name Hiroomi SAWADA
1st Author's Affiliation Graduate School of Science and Technology, Kumamoto University()
2nd Author's Name Morihiro KUGA
2nd Author's Affiliation Graduate School of Science and Technology, Kumamoto University
3rd Author's Name Toshinori SUEYOSHI
3rd Author's Affiliation Graduate School of Science and Technology, Kumamoto University
Date 2011-01-17
Paper # VLD2010-89,CPSY2010-44,RECONF2010-58
Volume (vol) vol.110
Number (no) 362
Page pp.pp.-
#Pages 6
Date of Issue