| Presentation | 2010-11-30 A wafer-level system integration technology for heterogeneous devices with pseudo-SoC Hiroshi YAMADA, Yutaka ONO〓KA, Atsuko IIDA, Kazuhiko ITAYA, Hideyuki FUNAKI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A wafer level system integration technology for heterogeneous devices has been developed by applying pseudo-SOC. The pseudo-SOC is designed to realize a single microchip with heterogeneous devices using individual processes, for epoxy resin, insulating layer, and redistribution layer, respectively. The KGD (Known Good Die) heterogeneous devices are embedded in the epoxy resin to reconfigure the reconfigured integration wafer. As the insulating layer and redistribution layer are formed by semiconductor wafer process without interposer substrate, the pseudo-SOC enables integration density as identical to that of SOC. This paper presents an overview of wafer level system integration technology for heterogeneous devices by applied pseudo-SoC and then focuses on the flexible pseudo-SOC which integrates optical MEMS and its driver CMOS-LSI for mobile electronics device applications. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Pseudo-SoC / Heterogeneous device / Wafer-level / System integration / Flexible |
| Paper # | CPM2010-135,ICD2010-94 |
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| Conference Information | |
| Committee | CPM |
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| Conference Date | 2010/11/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Component Parts and Materials (CPM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A wafer-level system integration technology for heterogeneous devices with pseudo-SoC |
| Sub Title (in English) | |
| Keyword(1) | Pseudo-SoC |
| Keyword(2) | Heterogeneous device |
| Keyword(3) | Wafer-level |
| Keyword(4) | System integration |
| Keyword(5) | Flexible |
| 1st Author's Name | Hiroshi YAMADA |
| 1st Author's Affiliation | Corporate R&D Center, Toshiba Corporation() |
| 2nd Author's Name | Yutaka ONO〓KA |
| 2nd Author's Affiliation | Corporate R&D Center, Toshiba Corporation |
| 3rd Author's Name | Atsuko IIDA |
| 3rd Author's Affiliation | Corporate R&D Center, Toshiba Corporation |
| 4th Author's Name | Kazuhiko ITAYA |
| 4th Author's Affiliation | Corporate R&D Center, Toshiba Corporation |
| 5th Author's Name | Hideyuki FUNAKI |
| 5th Author's Affiliation | Corporate R&D Center, Toshiba Corporation |
| Date | 2010-11-30 |
| Paper # | CPM2010-135,ICD2010-94 |
| Volume (vol) | vol.110 |
| Number (no) | 314 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |