Presentation | 2010-11-30 System Performance Improvement Expected for 3D LSI Chip Stacking Integration Technology Masahiro AOYAGI, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | 3D LSI chip stacking integration technology using through-Si-via is very promising for future electronic hardware integration technology. Latest research activity and system performance improvement expected for 3D LSI chip stacking integration technology are discussed. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | 3D / LSI / Chip / Stacking / System / TSV / SOC / SiP |
Paper # | CPM2010-134,ICD2010-93 |
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Conference Information | |
Committee | CPM |
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Conference Date | 2010/11/22(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | |
Chair | |
Vice Chair | |
Secretary | |
Assistant |
Paper Information | |
Registration To | Component Parts and Materials (CPM) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | System Performance Improvement Expected for 3D LSI Chip Stacking Integration Technology |
Sub Title (in English) | |
Keyword(1) | 3D |
Keyword(2) | LSI |
Keyword(3) | Chip |
Keyword(4) | Stacking |
Keyword(5) | System |
Keyword(6) | TSV |
Keyword(7) | SOC |
Keyword(8) | SiP |
1st Author's Name | Masahiro AOYAGI |
1st Author's Affiliation | National Institute of Advanced Industrial Science and Technology, Nanoelectronics Institute() |
Date | 2010-11-30 |
Paper # | CPM2010-134,ICD2010-93 |
Volume (vol) | vol.110 |
Number (no) | 314 |
Page | pp.pp.- |
#Pages | 5 |
Date of Issue |