Presentation 2010-11-30
An estimation of a dynamic partial reconfiguration capability of a dynamic optically reconfigurable gate array
Amarjargal GUNDJALAM, Minoru WATANABE,
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Abstract(in English) We have been developing Optically Reconfigurable Gate Arrays (ORGAs) to realize a high-speed dynamic reconfiguration capability. Among such researches, we have proposed a dynamic ORGA architecture that can achieve a high gate count VLSI by removing the static configuration memory and using the junction capacitance of photodiodes as dynamic random access memory. We have conducted dynamic partial reconfiguration experiments for the Dynamic Optically Reconfigurable Gate Array (DORGA) architecture. Since the dynamic architecture uses photodiodes as dynamic random access memory to store a configuration context, the retention time varies according to the repetition rate of partial dynamic reconfiguration procedures. Thus, we have analyzed the affection.
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Keyword(in English) Optically Reconfigurable Gate Arrays (ORGAs) / Partial reconfiguration / Holographic memories
Paper # CPM2010-133,ICD2010-92
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Committee CPM
Conference Date 2010/11/22(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An estimation of a dynamic partial reconfiguration capability of a dynamic optically reconfigurable gate array
Sub Title (in English)
Keyword(1) Optically Reconfigurable Gate Arrays (ORGAs)
Keyword(2) Partial reconfiguration
Keyword(3) Holographic memories
1st Author's Name Amarjargal GUNDJALAM
1st Author's Affiliation Faculty of Engineering, Shizuoka University()
2nd Author's Name Minoru WATANABE
2nd Author's Affiliation Faculty of Engineering, Shizuoka University
Date 2010-11-30
Paper # CPM2010-133,ICD2010-92
Volume (vol) vol.110
Number (no) 314
Page pp.pp.-
#Pages 6
Date of Issue