| Presentation | 2010/11/23 TFT SRAMを用いた3D-FPGAの開発(デザインガイア2010 : VLSI設計の新しい大地) / /, / /, / /, / /, Madurawe Raminda /, Sheldon Wu, / /, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Monolithically integrated Thin-Film-Transistor (TFT) SRAM configuration circuits over 90nm 9 layers of Cu interconnect CMOS is successfully fabricated at 300mm LSI mass production line for 3-dimensional Field Programmable Gate Arrays (3D-FPGA). This novel technology built over the 9th layer of Cu metal features aggressively scaled amorphous Si TFT having 180nm transistor gate length, 20nm gate oxide, fully silicided gate, S/D, all below 400C processing essential to not impact underlying Cu interconnects. Low temperature TFT devices show excellent NTFT/PTFT transistor lon/loff ratios over 2000/100 respectively, operate at 3.3V, E-field scalable, and are stable for SRAM configuration circuits. We believe this 3D-TFT technology is a major breakthrough innovation to overcome the conventional CMOS device shrinking limitation. |
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| Paper # | RECONF-2010-50 |
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| Committee | RECONF |
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| Conference Date | 2010/11/23(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
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| 5th Author's Name | Madurawe Raminda / |
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| 6th Author's Name | Sheldon Wu |
| 6th Author's Affiliation | readyASlC Inc. |
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| 7th Author's Affiliation | China International Intellectual Property Services Ltd. |
| Date | 2010/11/23 |
| Paper # | RECONF-2010-50 |
| Volume (vol) | vol.110 |
| Number (no) | 319 |
| Page | pp.pp.- |
| #Pages | 5 |
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