Presentation 2010/11/23
An Effective Processing Method for Parallel Loops on FPGA with PCI-Express
Koichi ARAKI, Yukinori SATO, Yasushi INOGUCHI,
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Abstract(in English) As FPGAs with a PCI-Express Interface appear in the market, the data transter speed between an FPGA and other units, such as CPUs and Memories, is increased However, if the HW execution time is longer than the data transfer time, the data transfer is suspended to wait the HW execution. Therefore, the data transfer speed decreases. In this paper, we propose a ReST which can process a data parallel loop using an FPGA without suspending the data transfer. We present a ReST framework, which generates the HW structure of the ReST. As a result of performance evaluation, we show that the ReST structure using the ReST framework performs well in terms of the Hi-speed data transfer and the the HW execution on the FPGA.
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Keyword(in English) PCI-Express / Impulse C / Data Parallelism / FPGA
Paper # RECONF-2010-47
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Conference Information
Committee RECONF
Conference Date 2010/11/23(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An Effective Processing Method for Parallel Loops on FPGA with PCI-Express
Sub Title (in English)
Keyword(1) PCI-Express
Keyword(2) Impulse C
Keyword(3) Data Parallelism
Keyword(4) FPGA
1st Author's Name Koichi ARAKI
1st Author's Affiliation School of Information Science Japan Advanced Institute of Science and Technology()
2nd Author's Name Yukinori SATO
2nd Author's Affiliation Center for Information Science Japan Advanced Institute of Science and Technology
3rd Author's Name Yasushi INOGUCHI
3rd Author's Affiliation Center for Information Science Japan Advanced Institute of Science and Technology
Date 2010/11/23
Paper # RECONF-2010-47
Volume (vol) vol.110
Number (no) 319
Page pp.pp.-
#Pages 6
Date of Issue