| Presentation | 2010/11/23 Power-Consumption-Evaluation on the Pattern-Recognition Machine Using Data-Direct-Implementation Approach Yusuke SATO, Moritoshi YASUNAGA, Noriyuki AIBE, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, high-speed recognition systems are required in various situations in life. In order to reply the requirements, we have proposed a novel architecture called "Direct Data Implementation (DDI)". DDI is composed of dedicated circuits that have the same parallelism as the sample patterns by embedding known patterns directly to logic circuits. In this paper, we evaluated the power consumption of DDI. Systems using FPGAs have the peripheral circuits. Therefore, it is difficult to measure the power consumption of FPGAs accurately. In this paper, we have developed a dedicated measurement board and showed that the board can measure power consumption of the basis circuits using FPGAs precisely. We measured the power consumption of DDI implemented in the FPGAs on the board. As a result, we have found that DDI only requires about 1/280 of the energy that is required in the traditional sequential pattern recognition circuit. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Pattern Recognition / Parallel Processing / Power Consumption |
| Paper # | RECONF-2010-44 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2010/11/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Power-Consumption-Evaluation on the Pattern-Recognition Machine Using Data-Direct-Implementation Approach |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Pattern Recognition |
| Keyword(3) | Parallel Processing |
| Keyword(4) | Power Consumption |
| 1st Author's Name | Yusuke SATO |
| 1st Author's Affiliation | Graduate School of Systems and Information Engineering, University of Tsukuba() |
| 2nd Author's Name | Moritoshi YASUNAGA |
| 2nd Author's Affiliation | Graduate School of Systems and Information Engineering, University of Tsukuba |
| 3rd Author's Name | Noriyuki AIBE |
| 3rd Author's Affiliation | Graduate School of Systems and Information Engineering, University of Tsukuba |
| Date | 2010/11/23 |
| Paper # | RECONF-2010-44 |
| Volume (vol) | vol.110 |
| Number (no) | 319 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |