Presentation 2010/11/23
An FPGA Implementation of CRC Slicing-by-N algorithms
Amila AKAGIC, Hideharu AMANO,
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Abstract(in English) Cyclic Redundancy Check (CRC) is an error detection scheme that detects corruption of digital content during data transmission, processing or storage. The process of calculating the CRC values of a large amounts of data is most computationally intensive process when processing a protocol. The proposed software solutions are not able to generate CRC values at a very high speed (10 Gbps or higher), due to the limitations of current speed of processors. This paper examines new computer architectures for accelerating the process of calculating CRC using programmable logic - FPGA. Our hardware implementation was based on a newly proposed "Slicing-by-N" CRC algorithms that are using multiple tables and reading 32, 64, 128 and 256 bits at a time. We examine achievable clock speed, throughput and area utilization.
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Keyword(in English) Cyclic Redundancy Check (CRC) / FPGA / VHDL / network processing / field programmable
Paper # RECONF-2010-42
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Committee RECONF
Conference Date 2010/11/23(1days)
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Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An FPGA Implementation of CRC Slicing-by-N algorithms
Sub Title (in English)
Keyword(1) Cyclic Redundancy Check (CRC)
Keyword(2) FPGA
Keyword(3) VHDL
Keyword(4) network processing
Keyword(5) field programmable
1st Author's Name Amila AKAGIC
1st Author's Affiliation Dept. of ICS, KEIO University()
2nd Author's Name Hideharu AMANO
2nd Author's Affiliation Dept. of ICS, KEIO University
Date 2010/11/23
Paper # RECONF-2010-42
Volume (vol) vol.110
Number (no) 319
Page pp.pp.-
#Pages 6
Date of Issue