| Presentation | 2010-12-01 Sharing of Clock Gating Modules under Multi-Stage Clock Gating Control Xin MAN, Takashi HORIYAMA, Tomoo KIMURA, Koji KAI, Shinji KIMURA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Clock gating is an effective technique to reduce dynamic power consumption for sequential circuits. This paper shows a sharing method of clock gating logic under multi-stage clock gating control. By sharing the clock gating logic, the total activity of registers and clock gating modules can be reduced. The method is implemented based on BDD and is applied to counters and a set of benchmark circuits. There have been found on average 23.0% cost reduction by the proposed multi-stage clock gating generation method. The power estimation using layout data will also be shown. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | dynamic power reduction / automatic clock gating generation / multi-stage clock gating / BDD |
| Paper # | VLD2010-83,DC2010-50 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2010/11/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Sharing of Clock Gating Modules under Multi-Stage Clock Gating Control |
| Sub Title (in English) | |
| Keyword(1) | dynamic power reduction |
| Keyword(2) | automatic clock gating generation |
| Keyword(3) | multi-stage clock gating |
| Keyword(4) | BDD |
| 1st Author's Name | Xin MAN |
| 1st Author's Affiliation | Grad. School of Information, Production and System, Waseda University() |
| 2nd Author's Name | Takashi HORIYAMA |
| 2nd Author's Affiliation | Grad. School of Science and Technology, Saitama University |
| 3rd Author's Name | Tomoo KIMURA |
| 3rd Author's Affiliation | R&D Platform Development Center, Panasonic Corporation |
| 4th Author's Name | Koji KAI |
| 4th Author's Affiliation | R&D Platform Development Center, Panasonic Corporation |
| 5th Author's Name | Shinji KIMURA |
| 5th Author's Affiliation | Grad. School of Information, Production and System, Waseda University |
| Date | 2010-12-01 |
| Paper # | VLD2010-83,DC2010-50 |
| Volume (vol) | vol.110 |
| Number (no) | 317 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |