| Presentation | 2010-12-01 Optimal Adder Architecture in Ultra Low Voltage Domain Nao KONISHI, Masaru KUDO, Kimiyoshi USAMI, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Circuit performance is evaluated for several adder architectures with wiring capacitance extracted from layout at 65nm process. The voltage for the minimum energy is 0.3V, and doesn't change even with the additional wiring capacitance. Optimal adder architecture that gives the minimum energy differs depending on the target delay. KSA is the optimal adder for 0.6ns and shorter delay, CLA is the optimal for less than 1.1ns, and RCA achieves the minimum energy for 1.1ns and longer delay. The best energy performance is RCA. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Adder / Ultra Low Voltage / Low Power Technique |
| Paper # | VLD2010-81,DC2010-48 |
| Date of Issue |
| Conference Information | |
| Committee | DC |
|---|---|
| Conference Date | 2010/11/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Dependable Computing (DC) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Optimal Adder Architecture in Ultra Low Voltage Domain |
| Sub Title (in English) | |
| Keyword(1) | Adder |
| Keyword(2) | Ultra Low Voltage |
| Keyword(3) | Low Power Technique |
| 1st Author's Name | Nao KONISHI |
| 1st Author's Affiliation | Department of Information Science and Engineering, Shibaura Institute of Technology() |
| 2nd Author's Name | Masaru KUDO |
| 2nd Author's Affiliation | Department of Information Science and Engineering, Shibaura Institute of Technology |
| 3rd Author's Name | Kimiyoshi USAMI |
| 3rd Author's Affiliation | Department of Information Science and Engineering, Shibaura Institute of Technology |
| Date | 2010-12-01 |
| Paper # | VLD2010-81,DC2010-48 |
| Volume (vol) | vol.110 |
| Number (no) | 317 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |