| Presentation | 2010-12-01 Develop A Clock Tree Generator into Open-source CAD System Takuya HIGUCHI, Jun'ichiro OGANE, Naohiko SHIMIZU, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We developed the LSI design methodology with using NSL which is a high-level hardware description language, and Alliance CAD System which is EDA tools with scalable cell library.[1] We made "on semi 1.2μm" process and Rohm 0.35μm, which are sub micron and deep-sub micron process. However, because of simply routing clock signals without consideration of digital system performance, there is the problem clock skew caused by RC delay on deep-sub micron process. In order to solve this problem, the authors implement the function clock tree synthesis as part of toolchain into Alliance. |
| Keyword(in Japanese) | (See Japanese page) |
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| Paper # | VLD2010-80,DC2010-47 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2010/11/22(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Develop A Clock Tree Generator into Open-source CAD System |
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| 1st Author's Name | Takuya HIGUCHI |
| 1st Author's Affiliation | Course of Computer and Communications, Graduate School of Engineering, Tokai University() |
| 2nd Author's Name | Jun'ichiro OGANE |
| 2nd Author's Affiliation | Course of Computer and Communications, Graduate School of Engineering, Tokai University |
| 3rd Author's Name | Naohiko SHIMIZU |
| 3rd Author's Affiliation | Department of Embedded Technology, School of Information Science and Technology, Tokai University |
| Date | 2010-12-01 |
| Paper # | VLD2010-80,DC2010-47 |
| Volume (vol) | vol.110 |
| Number (no) | 317 |
| Page | pp.pp.- |
| #Pages | 6 |
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