Presentation 2010-12-01
A Sequential Test Generation Method and a Binding Method for Testability Using Behavioral Description
Ryoichi INOUE, Hiroaki FUJIWARA, Toshinori HOSOKAWA, Hideo FUJIWARA,
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Abstract(in English) Although many works on test generation algorithms for sequential circuits have been reported so far, it is still very hard to achieve high fault coverage because of the complexity of sequential test generation. Several test generation methods using behavioral description and functional register transfer level (RTL) circuits at high level have been proposed to accelerate test generation time. Among them, there are works on test generation methods for assignment decision diagrams (ADDs) that represent functional RTL circuits. However, the test sequence generated by those methods without considering resource binding cannot guarantee to achieve high fault coverage at gate level even if the test environment coverage at RTL is high. This paper proposes a test generation method that considers resource binding in order to achieve higher fault coverage than previous methods.
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Keyword(in English) Sequential test generation / behavioral synthesis / binding / test environment / assignment decision diagrams
Paper # VLD2010-76,DC2010-43
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Committee DC
Conference Date 2010/11/22(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Sequential Test Generation Method and a Binding Method for Testability Using Behavioral Description
Sub Title (in English)
Keyword(1) Sequential test generation
Keyword(2) behavioral synthesis
Keyword(3) binding
Keyword(4) test environment
Keyword(5) assignment decision diagrams
1st Author's Name Ryoichi INOUE
1st Author's Affiliation Graduate School of Industrial Technology, Nihon University()
2nd Author's Name Hiroaki FUJIWARA
2nd Author's Affiliation Graduate School of Industrial Technology, Nihon University
3rd Author's Name Toshinori HOSOKAWA
3rd Author's Affiliation College of Industrial Technology, Nihon University
4th Author's Name Hideo FUJIWARA
4th Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology (NAIST)
Date 2010-12-01
Paper # VLD2010-76,DC2010-43
Volume (vol) vol.110
Number (no) 317
Page pp.pp.-
#Pages 6
Date of Issue