| Presentation | 2010-12-01 Evaluation and Verification of Dependable Processor Architecture Using System-Level Fault-Injection Scheme Yohei NAKATA, Yasuhiro ITO, Yasuo SUGURE, Shigeru OHO, Hiroko KAWAGUCHI, Masahiko YOSHIMOTO, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We develop a fault case generator that can generate memory failures in aprocessor-in-the-loop simulation. The fault injection system (FIS) generates memory failure patterns based on a transistor-level simulation and SRAM failure model. By using this FIS, processors with 6T normal SRAM and with 7T/14T dependable SRAM can be evaluated and compared. We confirmed that the dependable SRAM reduces abnormal terminations and improves a system-level dependability in a vehicle engine control system. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Fault-Injection / SRAM / Dependable Processor / System-Level Verification |
| Paper # | VLD2010-74,DC2010-41 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2010/11/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation and Verification of Dependable Processor Architecture Using System-Level Fault-Injection Scheme |
| Sub Title (in English) | |
| Keyword(1) | Fault-Injection |
| Keyword(2) | SRAM |
| Keyword(3) | Dependable Processor |
| Keyword(4) | System-Level Verification |
| 1st Author's Name | Yohei NAKATA |
| 1st Author's Affiliation | Graduate School of System Informatics, Kobe University() |
| 2nd Author's Name | Yasuhiro ITO |
| 2nd Author's Affiliation | Hitachi, Ltd. Central Research Laboratory |
| 3rd Author's Name | Yasuo SUGURE |
| 3rd Author's Affiliation | Hitachi, Ltd. Central Research Laboratory |
| 4th Author's Name | Shigeru OHO |
| 4th Author's Affiliation | Hitachi, Ltd. Central Research Laboratory |
| 5th Author's Name | Hiroko KAWAGUCHI |
| 5th Author's Affiliation | Graduate School of System Informatics, Kobe University |
| 6th Author's Name | Masahiko YOSHIMOTO |
| 6th Author's Affiliation | Graduate School of System Informatics, Kobe University:Japan Science and Technology Agencey, CREST |
| Date | 2010-12-01 |
| Paper # | VLD2010-74,DC2010-41 |
| Volume (vol) | vol.110 |
| Number (no) | 317 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |