| Presentation | 2010-12-01 SREEP : A Tool for Secure Scan Design Using Shift Register Equivalents Katsuya FUJIWARA, Hideo FUJIWARA, Hideo TAMAMOTO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | It is important to find an efficient design-for-testability methodology that satisfies both security and testability though there exists an inherent contradiction between security and testability for digital circuits. The authors reported a secure and testable scan design approach by using extended shift registers that are functionally equivalent but not structurally equivalent to shift registers, and clarified each cardinality of several classes of shift register equivalents (SR-equivalents) as well as the whole class of SR-equivalents. In this paper, we present a tool for secure scan design that generates secure scan circuits based on the proposed SR-equivalent method, shows their security level, and provides data necessary for scan-in/out operation during test generation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Design for Terstability / Secure Scan / Shift Register Equivalent / Equivalent Class |
| Paper # | VLD2010-72,DC2010-39 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2010/11/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | SREEP : A Tool for Secure Scan Design Using Shift Register Equivalents |
| Sub Title (in English) | |
| Keyword(1) | Design for Terstability |
| Keyword(2) | Secure Scan |
| Keyword(3) | Shift Register Equivalent |
| Keyword(4) | Equivalent Class |
| 1st Author's Name | Katsuya FUJIWARA |
| 1st Author's Affiliation | Department of Computer Science and Engineering, Akita University() |
| 2nd Author's Name | Hideo FUJIWARA |
| 2nd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| 3rd Author's Name | Hideo TAMAMOTO |
| 3rd Author's Affiliation | Department of Computer Science and Engineering, Akita University |
| Date | 2010-12-01 |
| Paper # | VLD2010-72,DC2010-39 |
| Volume (vol) | vol.110 |
| Number (no) | 317 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |