| Presentation | 2010-11-30 Accurate Delay Analysis Method of Power-Gated Circuit Seidai TAKEDA, Kyundong KIM, Hiroshi NAKAMURA, Kimiyoshi USAMI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We present a noble delay computation methodology for cluster-based power-gated circuit. Our scheme can compute circuit delay with high accuracy by using Dynamic Timing Analysis and considering nonlinear nature of virtual ground voltage drop. This scheme can drastically reduce pessimism of delay estimation than one of conventional method. Evaluation result shows that this scheme achieved 57 percentage point error reduction compared with conventional method on 3bit Ripple Carry Adder which contains 27% sleep transistor area. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Power Gating / MTCMOS / Gate Delay Model / IR Drop |
| Paper # | VLD2010-70,DC2010-37 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2010/11/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Accurate Delay Analysis Method of Power-Gated Circuit |
| Sub Title (in English) | |
| Keyword(1) | Power Gating |
| Keyword(2) | MTCMOS |
| Keyword(3) | Gate Delay Model |
| Keyword(4) | IR Drop |
| 1st Author's Name | Seidai TAKEDA |
| 1st Author's Affiliation | Graduate School of Engineering, The University of Tokyo() |
| 2nd Author's Name | Kyundong KIM |
| 2nd Author's Affiliation | Graduate School of Engineering, The University of Tokyo |
| 3rd Author's Name | Hiroshi NAKAMURA |
| 3rd Author's Affiliation | Graduate School of Information Science and Technology, The University of Tokyo |
| 4th Author's Name | Kimiyoshi USAMI |
| 4th Author's Affiliation | Department of Information Science and Engineering, Shibaura Institute of Technology |
| Date | 2010-11-30 |
| Paper # | VLD2010-70,DC2010-37 |
| Volume (vol) | vol.110 |
| Number (no) | 317 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |